The present application claims priority under 35 U.S.C. xc2xa7 119 from Korean patent application No. 2000-37659, xe2x80x9cIsolation Method for Single Crystalline Silicon Micro Structure Using Triple Layers,xe2x80x9d filed with the Korean Industrial Property Office on Jul. 3, 2000, which application is hereby incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to micromachining and in particular to electrically isolating parts of silicon microstructures.
2. Description of the Related Art
Microelectromechanical systems include component structures with typical minimum dimensions on the order of a micron where the component structures can have elaborate shapes and perform a variety of complex functions. The component structures of microelectromechanical systems are formed on a semiconductor or glass substrate. Microelectromechanical systems include devices such as accelerometers that sense the acceleration of a moving object, gyroscopes that sense the angular rate of a rotating object and mirror arrays that deflect light in fiber optic communication and display applications. Micromachining techniques are used to fabricate the very small structures that are integrated with electrical parts on the semiconductor or glass substrate. The techniques used to fabricate these microelectromechanical systems are largely based on semiconductor device fabricating technology, including photolithography, thin film deposition, etching, impurity doping by diffusion and ion implantation, electroplating and wafer bonding.
Microelectromechanical systems often include moving parts that are suspended from or tethered to an underlying substrate and that can move independently of the underlying substrate. Microelectromechanical systems also include electrodes that are electrically isolated to allow the electrodes, for example, to measure electrical signals flowing in the moving parts of the system. Other types of electrodes are used to apply electrical signals to the moving parts of the system; these electrodes are generally electrically isolated. Electrodes have to be electrically isolated from one another, and also from the substrate on which the electrodes and the tethered moving parts are fabricated. Many methods for electrically isolating a part of a microelectromechanical system from other parts of the system have been studied.
FIGS. 1a-1f shows process steps in the conventional isolation process known as the single crystalline reactive etching and metallization (hereinafter, referred to as the xe2x80x9cSCREAMxe2x80x9d) process. The SCREAM isolation process is performed on a structure fabricated by the SCREAM micromachining technique in the manner discussed in U.S. Pat. No. 5,563,343; U.S. Pat. No. 5,198,390; and K. A. Shaw, Z. L. Zhang, and N. C. MacDonald, xe2x80x9cSCREAM I: A Single Mask, Single-Crystal Silicon, Reactive Ion Etching Process for Microelectromechanical Structures,xe2x80x9d Sensors and Actuators A, Vol. 40, pp. 63, 1994. Plasma enhanced chemical vapor deposition (hereinafter, xe2x80x9cPECVDxe2x80x9d) covers all surfaces of a micromachined structure with an oxide film. Selective deposition of metal film on the structure forms electrodes and electrically conducting paths on top of the PECVD oxide film so that the PECVD oxide film separates the electrodes from the silicon substrate. In this SCREAM process, electrical isolation of the electrodes is achieved by depositing the metal film only on the top and the side surfaces of microelectromechanical structures that are covered by the PECVD oxide film.
The SCREAM isolation process has the advantage of being relatively simple in not requiring separate photolithography and etching steps once the structure is fabricated using the SCREAM micromachining technique. On the other hand, the coverage achieved in the deposition of the metal film is generally poor and hence the SCREAM isolation process typically cannot be applied to tall structures having a high aspect ratio. It should be noted that, if a metal or other material is deposited that has good step coverage, such as metal films deposited by low pressure chemical vapor deposition (hereinafter, referred to as xe2x80x9cLPCVDxe2x80x9d), all electrodes and microelectromechanical parts are electrically connected, and hence, electrical isolation is not achieved.
FIGS. 2a-2f shows the silicon on oxide insulator (hereinafter, xe2x80x9cSOIxe2x80x9d) wafer method, used in forming the microelectromechanical systems described in the following references: B. Diem, et al., xe2x80x9cSOI(SIMOX) as a Substrate for Surface Micromachining of Single Crystalline Silicon Sensors and Actuators,xe2x80x9d Tech. Dig. 7th Int. Conf. Solid-State Sensors and Actuators (Transducers ""93), Yokohama, Japan, 1993, pp. 233-236; and C. Marxer, et al., xe2x80x9cVertical Mirrors Fabricated by Deep Reactive Ion Etching for Fiber-Optic Switching Applications,xe2x80x9d IEEE/ASME Journal of Microelectromechanical Systems, Vol. 6, No. 3, pp. September 1997. In the SOI wafer method, the portion of the wafer on top of the buried oxide layer (hereinafter, the xe2x80x9cdevice layerxe2x80x9d) is highly doped, conducting silicon. Since all structures and electrodes are fabricated in the device layer and are defined by etching the device layer down to the buried oxide layer, electrical isolation of the resulting electrodes is achieved automatically. On the other hand, SOI wafers are generally expensive and the residual stress created by the buried oxide layer can warp and change the shape of microelectromechanical structures made on the surface layer. In addition, the micromachined portions of the device layer silicon near the oxide interface can have roughened features (produced by the xe2x80x9cfootingxe2x80x9d effect) when the structures and electrodes are formed in a deep plasma etching process. Another disadvantage of the SOI process is that the as-manufactured wafer has an established thickness of the oxide film and the device layer and these thicknesses cannot be modified once a wafer is manufactured.
FIG. 3 shows a scanning electron microscope (SEM) photograph of a micromachined comb-drive structure fabricated from single crystal silicon. The electrodes of the illustrated comb-drive structure are isolated using the junction isolation method. The junction isolation method is described, for example, in S. Lee, S. Park and D. Cho, xe2x80x9cThe Surface/Bulk Micromachining (SBM) Process: A New Method for Fabricating Released Microelectromechanical Systems in Single Crystal Silicon,xe2x80x9d IEEE/ASME J. Microelectromechanical Systems, Vol. 8, No. 4, December 1999. The junction isolation method forms a junction diode on a lightly doped N-type or P-type wafer. Applying a reverse biased voltage to the junction diode isolates the junction electrode from the substrate. Referring to FIG. 3, the silicon substrate is lightly doped P-type and the lighter parts, including the comb-drive structure, are highly doped N-type with phosphorus, so that a PN junction between the silicon substrate (P-type) and the electrode (N-type) is formed. In this case, if a reverse bias voltage is applied to the PN junction, the electrodes are electrically isolated from the silicon substrate. This method has the advantage that the isolation steps are done before the micromechanical structure is fabricated, so that the structure can be fabricated in a relatively easy manner and with relatively little of the stress created by the isolation method. On the other hand, the method has disadvantage that the depth of the PN junction often cannot be made sufficiently deep, so that this process usually is not readily applied to a tall structure having a high aspect ratio.
FIG. 4 is a structure formed by yet another conventional isolation method, the trench oxide isolation method, described in the following references: U.S. Pat. No. 5,930,595; U. Sridhar et al., xe2x80x9cTrench Oxide Isolated Single Crystal Silicon Micromachined Accelerometer,xe2x80x9d IEEE IEDM, San Francisco Calif., Dec. 6-9, 1998. pp. 475-478; and S. Lee, S. Park, D. Cho and Y. Oh xe2x80x9cSurface/Bulk Micromachining (SBM) Process and Deep Trench Oxide Isolation Method for MEMSxe2x80x9d, IEEE IEDM, Washington, D.C., Dec. 5-8, 1999. pp. 701-704. This trench isolation method includes forming U-shaped trenches 14 on a silicon substrate 16, forming thermal oxide layers 18 and depositing oxide layers 20 on all sides of the structure where the trenches are formed. The oxide films 18, 20 filling the trenches attach the electrode structures 22, 24 to the silicon substrate 16 through the respective sidewalls so that the oxide films support the electrodes and tethered structures. The oxide films electrically isolate the electrodes from each other and from the substrate.
This trench isolation method has the advantage that the method can be applied to a tall structure having a high aspect ratio. On the other hand, separate photolithography and etching steps are required to form a metal layer on the electrode to allow wire bonding the electrode to a package. Two different release processes are required: one to separate the electrode component from the substrate and a second to separate the structure part from the substrate. The trenches between the sidewalls of the electrode and the sidewalls of the substrate generally cannot be made arbitrarily large, as would be desired to achieve a small parasitic capacitance, without sacrificing the structural rigidity of the trench filled oxide layers that support the structure and electrodes. Additionally, the conventional trench isolation method deposits the insulation layers on the sides of the electrode to support the structure and electrodes. Therefore, the electrode and the substrate need to be supported by means other than the insulating layers during manufacturing, which limits the electrode shapes that can be made. In particular, it is difficult to fabricate an electrode in an xe2x80x9cislandxe2x80x9d shape or in a complicated electrode arrangement like that used in an angular velocimeter. Those skilled in the art can appreciate the need for a simpler isolation method.
Accordingly, the present invention is directed to an isolation method for a microstructure that provides effective isolation in a range of applications.
An aspect of the present invention provides a method for forming an electrode in a micromachined structure. The method includes providing a microstructure comprising silicon, the microstructure having at least one released surface opposite and spaced from an underlying surface of a substrate comprising silicon. An insulation layer is formed over surfaces of the microstructure, including over the released surface, a conductive layer is formed over surfaces of the insulation layer, and a metal layer is formed over at least a top surface of the conductive layer on at least a portion of the microstructure.
Another preferred isolation method forms an insulation layer on the exposed surfaces of a microstructure after the microstructure has been formed by micromachining and released from the surface of an underlying substrate. The isolation method forms a conductive layer over the entire insulation layer and forms a metal layer over the conductive layer on top portions of the microstructure. Partially etching of the conductive layer forms electrical isolation between parts of the microstructure.
The conductive layer preferably may be a heavily-doped polycrystalline silicon layer having good step coverage formed by low pressure chemical vapor deposition (xe2x80x9cLPCVDxe2x80x9d). Etching of the conductive layer preferably may be accomplished by anisotropic dry etching. The insulation layer preferably may be a thermal oxide layer formed on the surface of a preferred single crystalline silicon by thermal oxidization. Alternatively, the insulation layer may be an oxide layer or a nitride layer formed by plasma enhanced chemical vapor deposition (xe2x80x9cPECVDxe2x80x9d) or LPCVD having good step coverage, or a composite insulation layer of a thermal oxide layer, an LPCVD oxide layer, an LPVCD nitride layer, a PECVD oxide layer and/or a PECVD nitride layer. Other insulators are apparent.
Another aspect of the invention provides a silicon microstructure having released structures and a layer structure for electrically isolating portions of the silicon microstructure. The layer structure comprises an insulation layer formed over released surfaces of the silicon microstructure, a conductive layer formed over the insulation layer including over sidewalls of the released structures, conductive layer having gaps electrically isolating portions of the silicon microstructure, and a metal layer formed over portions of the released structures.